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Monday, 28 April 2014

Difference Between CMOS and TTL Signals

by realfinetime  |  in TTL at  05:35

Characteristics of CMOS Logic.

CMOS logic gates dissipates less power : Power dissipation depends on the power supply voltage, frequency, output load and input rise time. At  1 MHz and 50 pF load, Each gate dissipates a typical power of  10nW.


Short propogation delays : Propogation delays are normally around 25nS - 50nS. It is dependant on the supply voltage.

Noise immunity approaches around 50% of the full Logic swing.

Levels of the Logic signals are approximately equal to the power supplied since the input impedance is too high.


Voltage levels range from 0 - VDD where VDD is the supply voltage and it varies from 4.75V - 5.25V. Voltage in the range 0 - 1/3 VDD V will be considered as LOW and voltage in the range 2/3 VDD  - VDD Vwill be considered as HIGH.


Characteristics of TTL logic.

Each gate dissipates around 10mW.

Propogation delays are normally 10nS when driving a 15pF/400 OHM load.

Voltage levels range from 0 - Vcc where Vcc is the supply voltage and it varies from 4.75V - 5.25V. Voltage in the range 0  - .8 V will be considered as LOW and voltage in the range 2V - Vcc will be considered as HIGH.

Comparison between CMOS and TTL logic.

CMOS components are more susceptible to damage from electrostatic discharge than TTL components.

Transmission of digital signals are simpler and less expensive with CMOS chips because of longer rise and fall times of Digital signals.

CMOS circuits consume less power compared to TTL circuits at rest. But the CMOS power consumption increases faster with high clock speeds than the TTL circuits. Lower power consumption requires less power distribution and requires simpler and cheaper circuit.

CMOS components are more expensive than TTL components. But on a system, CMOS components are less expensive due to smaller design and hence the lessser regulation.

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